Low power, ferroelectric memory and artificial intelligence logic for edge computing and control

The Internet of Things (IoT) needs intelligent, fast and energy efficient handling of sensory, inhomogeneous data that goes beyond current storage and data processing capabilities. In traditional computer architecture, data transfer between storage and processor, called the von Neumann bottleneck, is the major obstacle to low power, rapid computing, accounting for up to 90% of energy consumption. The solution to this is a radical shift to edge computing, i.e. computing at or near the sensor node where data is acquired and stored and constitutes a new paradigm in computer architecture. But, computing in memory (CiM) also poses new challenges for device and circuit performance. Edge processing must be rapid and reliable, for example, for image recognition in autonomous driving and other artificial intelligence applications, low power to preserve autonomy and protect the environment, as well as being cheap to produce. Ferroelectric memory and logic offer these opportunities. The polarization can be used to set logical states in ferroelectric field effect transistors (FeFETs) and binary states in non-volatile memory (NVM) cells. Switching the ferroelectric logic or memory state is intrinsically low-power, fast and, with respect to current silicon technologies, readily integrated into CMOS and therefore of low cost. For complex calculations, fast processing using deep neural networks has been applied to many fields such as computer vision. At the same time, the high computational complexity requires designing energy efficient hardware architectures for the edge. In both front-end (FEOL) and back-end (BEOL) of the line technological scenarios, the ferroelectric logic approach enables decoupling between programming (which can be slow) and data switch or processing (which has to be fast). For example, FeFETs can be programmed or configured once and then operated at speed in multiply-accumulate functions such as in image filters. We propose a demonstrator of a ferroelectric-based non-volatile low-power reconfigurable accelerator based on energy efficient spiked neural networks with unpredecented levels of granularity and combination of computing and NVM elements. Technically, we will optimize materials and technology for the critical components of a low power CiM microprocessor based on neuromorphic device engineering with embedded NVM. It will then develop solutions for two flagships applications: rapid, low power image filtering and secure logic for edge processing of MCUs. The basic aims of the project are thus well defined but the project requires the integration of additional competences in order achieve the objectives: transmission electron microscopy services, device modelling specialists, memory array designers, neuromorphic engineers, imaging experts for performance specifications and a European foundry for the FEOL. The search for the additional expert partners in their fields and their inclusion in the project will be possible thanks to the MRSEI funding. The funding will allow access to up to date, detailed market studies to detail the industrial and economic impacts of the project work and the organization of face-to-face meetings and conference participations during the intense preparatory period of proposal writing. The structuring of the network (10-11 partners) allowed by the MRSEI funding, will provide an operational collaborative working group for the project itself. Finally, The MRSEI funding will allow the CEA to engage a consultancy company, which is proven to substantially improve the form and organization of EU proposals and therefore optimize the chances of funding.